From f2583edf6b5b26d6e5525728f57befeca112d253 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Thu, 4 Jan 2024 12:02:43 +0000 Subject: [PATCH 0810/1085] drm/vc4: Fix reading of frame count on GEN5 / Pi4 The frame count values moved within registers DISPSTAT1 and DISPSTAT2 with GEN5, so update the accessor function to accommodate that. Fixes: b51cd7ad143d ("drm/vc4: hvs: Fix frame count register readout") Signed-off-by: Dave Stevenson --- drivers/gpu/drm/vc4/vc4_hvs.c | 23 +++++++++++++++++++++-- drivers/gpu/drm/vc4/vc4_regs.h | 6 ++++++ 2 files changed, 27 insertions(+), 2 deletions(-) --- a/drivers/gpu/drm/vc4/vc4_hvs.c +++ b/drivers/gpu/drm/vc4/vc4_hvs.c @@ -823,10 +823,28 @@ u8 vc4_hvs_get_fifo_frame_count(struct v if (!drm_dev_enter(drm, &idx)) return 0; - if (vc4->gen >= VC4_GEN_6) { + switch (vc4->gen) { + case VC4_GEN_6: field = VC4_GET_FIELD(HVS_READ(SCALER6_DISPX_STATUS(fifo)), SCALER6_DISPX_STATUS_FRCNT); - } else { + break; + case VC4_GEN_5: + switch (fifo) { + case 0: + field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), + SCALER5_DISPSTAT1_FRCNT0); + break; + case 1: + field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), + SCALER5_DISPSTAT1_FRCNT1); + break; + case 2: + field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2), + SCALER5_DISPSTAT2_FRCNT2); + break; + } + break; + case VC4_GEN_4: switch (fifo) { case 0: field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), @@ -841,6 +859,7 @@ u8 vc4_hvs_get_fifo_frame_count(struct v SCALER_DISPSTAT2_FRCNT2); break; } + break; } drm_dev_exit(idx); --- a/drivers/gpu/drm/vc4/vc4_regs.h +++ b/drivers/gpu/drm/vc4/vc4_regs.h @@ -424,6 +424,10 @@ # define SCALER_DISPSTAT1_FRCNT0_SHIFT 18 # define SCALER_DISPSTAT1_FRCNT1_MASK VC4_MASK(17, 12) # define SCALER_DISPSTAT1_FRCNT1_SHIFT 12 +# define SCALER5_DISPSTAT1_FRCNT0_MASK VC4_MASK(25, 20) +# define SCALER5_DISPSTAT1_FRCNT0_SHIFT 20 +# define SCALER5_DISPSTAT1_FRCNT1_MASK VC4_MASK(19, 14) +# define SCALER5_DISPSTAT1_FRCNT1_SHIFT 14 #define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \ (x) * (SCALER_DISPSTAT1 - \ @@ -442,6 +446,8 @@ #define SCALER_DISPSTAT2 0x00000068 # define SCALER_DISPSTAT2_FRCNT2_MASK VC4_MASK(17, 12) # define SCALER_DISPSTAT2_FRCNT2_SHIFT 12 +# define SCALER5_DISPSTAT2_FRCNT2_MASK VC4_MASK(19, 14) +# define SCALER5_DISPSTAT2_FRCNT2_SHIFT 14 #define SCALER_DISPBASE2 0x0000006c #define SCALER_DISPALPHA2 0x00000070