From 4fe131368be6d89499a52a53f4043f4d92f1956b Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Fri, 5 Apr 2024 17:40:05 +0100 Subject: [PATCH 1066/1085] drm/vc4: Add vblank callback to DSI0 to reset FIFO The pixel to byte FIFO appears to not always reset correctly, which can lead to colour errors and/or horizontal shifts. Reset on every vblank to work around the issue. Signed-off-by: Dave Stevenson --- drivers/gpu/drm/vc4/vc4_dsi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) --- a/drivers/gpu/drm/vc4/vc4_dsi.c +++ b/drivers/gpu/drm/vc4/vc4_dsi.c @@ -1438,6 +1438,15 @@ static const struct drm_bridge_funcs vc4 .mode_fixup = vc4_dsi_bridge_mode_fixup, }; +static void vc4_dsi_reset_fifo(struct drm_encoder *encoder) +{ + struct vc4_dsi *dsi = to_vc4_dsi(encoder); + u32 val; + + val = DSI_PORT_READ(CTRL); + DSI_PORT_WRITE(CTRL, val | DSI0_CTRL_CLR_PBCF); +} + static int vc4_dsi_late_register(struct drm_encoder *encoder) { struct drm_device *drm = encoder->dev; @@ -1682,6 +1691,9 @@ static int vc4_dsi_bind(struct device *d dsi->encoder.type = dsi->variant->port ? VC4_ENCODER_TYPE_DSI1 : VC4_ENCODER_TYPE_DSI0; + if (dsi->encoder.type == VC4_ENCODER_TYPE_DSI0) + dsi->encoder.vblank = vc4_dsi_reset_fifo; + dsi->regs = vc4_ioremap_regs(pdev, 0); if (IS_ERR(dsi->regs)) return PTR_ERR(dsi->regs);