// SPDX-License-Identifier: GPL-2.0 /* * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c * * Copyright (C) 2005, Intec Automation Inc. * Copyright (C) 2014, Freescale Semiconductor, Inc. * * Synced from Linux v4.19 */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include "sf_internal.h" /* Define max times to check status register before we give up. */ /* * For everything but full-chip erase; probably could be much smaller, but kept * around for safety for now */ #define HZ CONFIG_SYS_HZ #define DEFAULT_READY_WAIT_JIFFIES (40UL * HZ) static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op *op, void *buf) { if (op->data.dir == SPI_MEM_DATA_IN) op->data.buf.in = buf; else op->data.buf.out = buf; return spi_mem_exec_op(nor->spi, op); } static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len) { struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(code, 1), SPI_MEM_OP_NO_ADDR, SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_DATA_IN(len, NULL, 1)); int ret; ret = spi_nor_read_write_reg(nor, &op, val); if (ret < 0) { /* * spi_slave does not have a struct udevice member without DM, * so use the bus and cs instead. */ #if CONFIG_IS_ENABLED(DM_SPI) dev_dbg(nor->spi->dev, "error %d reading %x\n", ret, code); #else log_debug("spi%u.%u: error %d reading %x\n", nor->spi->bus, nor->spi->cs, ret, code); #endif } return ret; } static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) { struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 1), SPI_MEM_OP_NO_ADDR, SPI_MEM_OP_NO_DUMMY, SPI_MEM_OP_DATA_OUT(len, NULL, 1)); return spi_nor_read_write_reg(nor, &op, buf); } static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u_char *buf) { struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1), SPI_MEM_OP_ADDR(nor->addr_width, from, 1), SPI_MEM_OP_DUMMY(nor->read_dummy, 1), SPI_MEM_OP_DATA_IN(len, buf, 1)); size_t remaining = len; int ret; /* get transfer protocols. */ op.cmd.buswidth = spi_nor_get_protocol_inst_nbits(nor->read_proto); op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->read_proto); op.dummy.buswidth = op.addr.buswidth; op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->read_proto); /* convert the dummy cycles to the number of bytes */ op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; while (remaining) { op.data.nbytes = remaining < UINT_MAX ? remaining : UINT_MAX; ret = spi_mem_adjust_op_size(nor->spi, &op); if (ret) return ret; ret = spi_mem_exec_op(nor->spi, &op); if (ret) return ret; op.addr.val += op.data.nbytes; remaining -= op.data.nbytes; op.data.buf.in += op.data.nbytes; } return len; } #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) /* * Read configuration register, returning its value in the * location. Return the configuration register value. * Returns negative if error occurred. */ static int read_cr(struct spi_nor *nor) { int ret; u8 val; ret = spi_nor_read_reg(nor, SPINOR_OP_RDCR, &val, 1); if (ret < 0) { dev_dbg(nor->dev, "error %d reading CR\n", ret); return ret; } return val; } #endif /* * Write status register 1 byte * Returns negative if error occurred. */ static inline int write_sr(struct spi_nor *nor, u8 val) { nor->cmd_buf[0] = val; return spi_nor_write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1); } /* * Set write enable latch with Write Enable command. * Returns negative if error occurred. */ static inline int write_enable(struct spi_nor *nor) { return spi_nor_write_reg(nor, SPINOR_OP_WREN, NULL, 0); } /* * Send write disable instruction to the chip. */ static inline int write_disable(struct spi_nor *nor) { return spi_nor_write_reg(nor, SPINOR_OP_WRDI, NULL, 0); } static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd) { return mtd->priv; } static u8 spi_nor_convert_opcode(u8 opcode, const u8 table[][2], size_t size) { size_t i; for (i = 0; i < size; i++) if (table[i][0] == opcode) return table[i][1]; /* No conversion found, keep input op code. */ return opcode; } static inline u8 spi_nor_convert_3to4_read(u8 opcode) { static const u8 spi_nor_3to4_read[][2] = { { SPINOR_OP_READ, SPINOR_OP_READ_4B }, { SPINOR_OP_READ_FAST, SPINOR_OP_READ_FAST_4B }, { SPINOR_OP_READ_1_1_2, SPINOR_OP_READ_1_1_2_4B }, { SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B }, { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, }; return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, ARRAY_SIZE(spi_nor_3to4_read)); } static void spi_nor_set_4byte_opcodes(struct spi_nor *nor, const struct flash_info *info) { nor->read_opcode = spi_nor_convert_3to4_read(nor->read_opcode); } /* Enable/disable 4-byte addressing mode. */ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info, int enable) { int status; bool need_wren = false; u8 cmd; switch (JEDEC_MFR(info)) { case SNOR_MFR_ST: case SNOR_MFR_MICRON: /* Some Micron need WREN command; all will accept it */ need_wren = true; case SNOR_MFR_MACRONIX: case SNOR_MFR_WINBOND: if (need_wren) write_enable(nor); cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B; status = spi_nor_write_reg(nor, cmd, NULL, 0); if (need_wren) write_disable(nor); if (!status && !enable && JEDEC_MFR(info) == SNOR_MFR_WINBOND) { /* * On Winbond W25Q256FV, leaving 4byte mode causes * the Extended Address Register to be set to 1, so all * 3-byte-address reads come from the second 16M. * We must clear the register to enable normal behavior. */ write_enable(nor); nor->cmd_buf[0] = 0; spi_nor_write_reg(nor, SPINOR_OP_WREAR, nor->cmd_buf, 1); write_disable(nor); } return status; default: /* Spansion style */ nor->cmd_buf[0] = enable << 7; return spi_nor_write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1); } } #if defined(CONFIG_SPI_FLASH_SPANSION) || \ defined(CONFIG_SPI_FLASH_WINBOND) || \ defined(CONFIG_SPI_FLASH_MACRONIX) /* * Read the status register, returning its value in the location * Return the status register value. * Returns negative if error occurred. */ static int read_sr(struct spi_nor *nor) { int ret; u8 val; ret = spi_nor_read_reg(nor, SPINOR_OP_RDSR, &val, 1); if (ret < 0) { pr_debug("error %d reading SR\n", (int)ret); return ret; } return val; } /* * Read the flag status register, returning its value in the location * Return the status register value. * Returns negative if error occurred. */ static int read_fsr(struct spi_nor *nor) { int ret; u8 val; ret = spi_nor_read_reg(nor, SPINOR_OP_RDFSR, &val, 1); if (ret < 0) { pr_debug("error %d reading FSR\n", ret); return ret; } return val; } static int spi_nor_sr_ready(struct spi_nor *nor) { int sr = read_sr(nor); if (sr < 0) return sr; return !(sr & SR_WIP); } static int spi_nor_fsr_ready(struct spi_nor *nor) { int fsr = read_fsr(nor); if (fsr < 0) return fsr; return fsr & FSR_READY; } static int spi_nor_ready(struct spi_nor *nor) { int sr, fsr; sr = spi_nor_sr_ready(nor); if (sr < 0) return sr; fsr = nor->flags & SNOR_F_USE_FSR ? spi_nor_fsr_ready(nor) : 1; if (fsr < 0) return fsr; return sr && fsr; } /* * Service routine to read status register until ready, or timeout occurs. * Returns non-zero if error. */ static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor, unsigned long timeout) { unsigned long timebase; int ret; timebase = get_timer(0); while (get_timer(timebase) < timeout) { ret = spi_nor_ready(nor); if (ret < 0) return ret; if (ret) return 0; } dev_err(nor->dev, "flash operation timed out\n"); return -ETIMEDOUT; } static int spi_nor_wait_till_ready(struct spi_nor *nor) { return spi_nor_wait_till_ready_with_timeout(nor, DEFAULT_READY_WAIT_JIFFIES); } #endif /* CONFIG_SPI_FLASH_SPANSION */ /* * Erase an address range on the nor chip. The address range may extend * one or more erase sectors. Return an error is there is a problem erasing. */ static int spi_nor_erase_tiny(struct mtd_info *mtd, struct erase_info *instr) { return -ENOTSUPP; } static const struct flash_info *spi_nor_read_id(struct spi_nor *nor) { int tmp; u8 id[SPI_NOR_MAX_ID_LEN]; const struct flash_info *info; tmp = spi_nor_read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN); if (tmp < 0) { dev_dbg(nor->dev, "error %d reading JEDEC ID\n", tmp); return ERR_PTR(tmp); } info = spi_nor_ids; for (; info->sector_size != 0; info++) { if (info->id_len) { if (!memcmp(info->id, id, info->id_len)) return info; } } dev_dbg(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n", id[0], id[1], id[2]); return ERR_PTR(-EMEDIUMTYPE); } static int spi_nor_read_tiny(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf) { struct spi_nor *nor = mtd_to_spi_nor(mtd); int ret; dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len); while (len) { loff_t addr = from; ret = spi_nor_read_data(nor, addr, len, buf); if (ret == 0) { /* We shouldn't see 0-length reads */ ret = -EIO; goto read_err; } if (ret < 0) goto read_err; *retlen += ret; buf += ret; from += ret; len -= ret; } ret = 0; read_err: return ret; } /* * Write an address range to the nor chip. Data must be written in * FLASH_PAGESIZE chunks. The address range may be any size provided * it is within the physical boundaries. */ static int spi_nor_write_tiny(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen, const u_char *buf) { return -ENOTSUPP; } #ifdef CONFIG_SPI_FLASH_MACRONIX /** * macronix_quad_enable() - set QE bit in Status Register. * @nor: pointer to a 'struct spi_nor' * * Set the Quad Enable (QE) bit in the Status Register. * * bit 6 of the Status Register is the QE bit for Macronix like QSPI memories. * * Return: 0 on success, -errno otherwise. */ static int macronix_quad_enable(struct spi_nor *nor) { int ret, val; val = read_sr(nor); if (val < 0) return val; if (val & SR_QUAD_EN_MX) return 0; write_enable(nor); write_sr(nor, val | SR_QUAD_EN_MX); ret = spi_nor_wait_till_ready(nor); if (ret) return ret; ret = read_sr(nor); if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) { dev_err(nor->dev, "Macronix Quad bit not set\n"); return -EINVAL; } return 0; } #endif #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) /* * Write status Register and configuration register with 2 bytes * The first byte will be written to the status register, while the * second byte will be written to the configuration register. * Return negative if error occurred. */ static int write_sr_cr(struct spi_nor *nor, u8 *sr_cr) { int ret; write_enable(nor); ret = spi_nor_write_reg(nor, SPINOR_OP_WRSR, sr_cr, 2); if (ret < 0) { dev_dbg(nor->dev, "error while writing configuration register\n"); return -EINVAL; } ret = spi_nor_wait_till_ready(nor); if (ret) { dev_dbg(nor->dev, "timeout while writing configuration register\n"); return ret; } return 0; } /** * spansion_read_cr_quad_enable() - set QE bit in Configuration Register. * @nor: pointer to a 'struct spi_nor' * * Set the Quad Enable (QE) bit in the Configuration Register. * This function should be used with QSPI memories supporting the Read * Configuration Register (35h) instruction. * * bit 1 of the Configuration Register is the QE bit for Spansion like QSPI * memories. * * Return: 0 on success, -errno otherwise. */ static int spansion_read_cr_quad_enable(struct spi_nor *nor) { u8 sr_cr[2]; int ret; /* Check current Quad Enable bit value. */ ret = read_cr(nor); if (ret < 0) { dev_dbg(nor->dev, "error while reading configuration register\n"); return -EINVAL; } if (ret & CR_QUAD_EN_SPAN) return 0; sr_cr[1] = ret | CR_QUAD_EN_SPAN; /* Keep the current value of the Status Register. */ ret = read_sr(nor); if (ret < 0) { dev_dbg(nor->dev, "error while reading status register\n"); return -EINVAL; } sr_cr[0] = ret; ret = write_sr_cr(nor, sr_cr); if (ret) return ret; /* Read back and check it. */ ret = read_cr(nor); if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) { dev_dbg(nor->dev, "Spansion Quad bit not set\n"); return -EINVAL; } return 0; } #endif /* CONFIG_SPI_FLASH_SPANSION */ static void spi_nor_set_read_settings(struct spi_nor_read_command *read, u8 num_mode_clocks, u8 num_wait_states, u8 opcode, enum spi_nor_protocol proto) { read->num_mode_clocks = num_mode_clocks; read->num_wait_states = num_wait_states; read->opcode = opcode; read->proto = proto; } static int spi_nor_init_params(struct spi_nor *nor, const struct flash_info *info, struct spi_nor_flash_parameter *params) { /* (Fast) Read settings. */ params->hwcaps.mask = SNOR_HWCAPS_READ; spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ], 0, 0, SPINOR_OP_READ, SNOR_PROTO_1_1_1); if (!(info->flags & SPI_NOR_NO_FR)) { params->hwcaps.mask |= SNOR_HWCAPS_READ_FAST; spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_FAST], 0, 8, SPINOR_OP_READ_FAST, SNOR_PROTO_1_1_1); #ifdef CONFIG_SPI_FLASH_SPANSION if (JEDEC_MFR(info) == SNOR_MFR_CYPRESS && (info->id[1] == 0x2a || info->id[1] == 0x2b)) /* 0x2a: S25HL (QSPI, 3.3V), 0x2b: S25HS (QSPI, 1.8V) */ params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; #endif } if (info->flags & SPI_NOR_QUAD_READ) { params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], 0, 8, SPINOR_OP_READ_1_1_4, SNOR_PROTO_1_1_4); } return 0; } static int spi_nor_select_read(struct spi_nor *nor, const struct spi_nor_flash_parameter *params, u32 shared_hwcaps) { int best_match = shared_hwcaps & SNOR_HWCAPS_READ_MASK; int cmd; const struct spi_nor_read_command *read; if (best_match < 0) return -EINVAL; if (best_match & SNOR_HWCAPS_READ_1_1_4) cmd = SNOR_CMD_READ_1_1_4; else if (best_match & SNOR_HWCAPS_READ_FAST) cmd = SNOR_CMD_READ_FAST; else cmd = SNOR_CMD_READ; read = ¶ms->reads[cmd]; nor->read_opcode = read->opcode; nor->read_proto = read->proto; /* * In the spi-nor framework, we don't need to make the difference * between mode clock cycles and wait state clock cycles. * Indeed, the value of the mode clock cycles is used by a QSPI * flash memory to know whether it should enter or leave its 0-4-4 * (Continuous Read / XIP) mode. * eXecution In Place is out of the scope of the mtd sub-system. * Hence we choose to merge both mode and wait state clock cycles * into the so called dummy clock cycles. */ nor->read_dummy = read->num_mode_clocks + read->num_wait_states; return 0; } static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, const struct spi_nor_flash_parameter *params, const struct spi_nor_hwcaps *hwcaps) { u32 shared_mask; int err; /* * Keep only the hardware capabilities supported by both the SPI * controller and the SPI flash memory. */ shared_mask = hwcaps->mask & params->hwcaps.mask; /* Select the (Fast) Read command. */ err = spi_nor_select_read(nor, params, shared_mask); if (err) { dev_dbg(nor->dev, "can't select read settings supported by both the SPI controller and memory.\n"); return err; } /* Enable Quad I/O if needed. */ if (spi_nor_get_protocol_width(nor->read_proto) == 4) { switch (JEDEC_MFR(info)) { #ifdef CONFIG_SPI_FLASH_MACRONIX case SNOR_MFR_MACRONIX: err = macronix_quad_enable(nor); break; #endif case SNOR_MFR_ST: case SNOR_MFR_MICRON: break; default: #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) /* Kept only for backward compatibility purpose. */ err = spansion_read_cr_quad_enable(nor); #endif break; } } if (err) { dev_dbg(nor->dev, "quad mode not supported\n"); return err; } return 0; } static int spi_nor_init(struct spi_nor *nor) { if (nor->addr_width == 4 && (JEDEC_MFR(nor->info) != SNOR_MFR_SPANSION) && !(nor->info->flags & SPI_NOR_4B_OPCODES)) { /* * If the RESET# pin isn't hooked up properly, or the system * otherwise doesn't perform a reset command in the boot * sequence, it's impossible to 100% protect against unexpected * reboots (e.g., crashes). Warn the user (or hopefully, system * designer) that this is bad. */ if (nor->flags & SNOR_F_BROKEN_RESET) printf("enabling reset hack; may not recover from unexpected reboots\n"); set_4byte(nor, nor->info, 1); } return 0; } int spi_nor_scan(struct spi_nor *nor) { struct spi_nor_flash_parameter params; const struct flash_info *info = NULL; struct mtd_info *mtd = &nor->mtd; struct spi_nor_hwcaps hwcaps = { .mask = SNOR_HWCAPS_READ | SNOR_HWCAPS_READ_FAST }; struct spi_slave *spi = nor->spi; int ret; /* Reset SPI protocol for all commands. */ nor->reg_proto = SNOR_PROTO_1_1_1; nor->read_proto = SNOR_PROTO_1_1_1; nor->write_proto = SNOR_PROTO_1_1_1; if (spi->mode & SPI_RX_QUAD) hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4; info = spi_nor_read_id(nor); if (IS_ERR_OR_NULL(info)) return PTR_ERR(info); /* Parse the Serial Flash Discoverable Parameters table. */ ret = spi_nor_init_params(nor, info, ¶ms); if (ret) return ret; mtd->name = "spi-flash"; mtd->dev = nor->dev; mtd->priv = nor; mtd->type = MTD_NORFLASH; mtd->writesize = 1; mtd->flags = MTD_CAP_NORFLASH; mtd->size = info->sector_size * info->n_sectors; mtd->_erase = spi_nor_erase_tiny; mtd->_read = spi_nor_read_tiny; mtd->_write = spi_nor_write_tiny; nor->size = mtd->size; if (info->flags & USE_FSR) nor->flags |= SNOR_F_USE_FSR; if (info->flags & USE_CLSR) nor->flags |= SNOR_F_USE_CLSR; if (info->flags & SPI_NOR_NO_FR) params.hwcaps.mask &= ~SNOR_HWCAPS_READ_FAST; /* * Configure the SPI memory: * - select op codes for (Fast) Read, Page Program and Sector Erase. * - set the number of dummy cycles (mode cycles + wait states). * - set the SPI protocols for register and memory accesses. * - set the Quad Enable bit if needed (required by SPI x-y-4 protos). */ ret = spi_nor_setup(nor, info, ¶ms, &hwcaps); if (ret) return ret; if (nor->addr_width) { /* already configured from SFDP */ } else if (info->addr_width) { nor->addr_width = info->addr_width; } else if (mtd->size > 0x1000000) { /* enable 4-byte addressing if the device exceeds 16MiB */ nor->addr_width = 4; if (JEDEC_MFR(info) == SNOR_MFR_SPANSION || info->flags & SPI_NOR_4B_OPCODES) spi_nor_set_4byte_opcodes(nor, info); } else { nor->addr_width = 3; } if (nor->addr_width > SPI_NOR_MAX_ADDR_WIDTH) { dev_dbg(nor->dev, "address width is too large: %u\n", nor->addr_width); return -EINVAL; } /* Send all the required SPI flash commands to initialize device */ nor->info = info; ret = spi_nor_init(nor); if (ret) return ret; return 0; } /* U-Boot specific functions, need to extend MTD to support these */ int spi_flash_cmd_get_sw_write_prot(struct spi_nor *nor) { return -ENOTSUPP; }