From 61e034cd7f7a66c61a791d86bb866c56067b599a Mon Sep 17 00:00:00 2001 From: Phil Elwell Date: Thu, 30 Nov 2023 12:57:03 +0000 Subject: [PATCH 0828/1085] pinctrl: bcm2712: Fix for the first valid GPIO A non-zero mux bit number is used to detect a valid entry in the pin_regs tables, but GPIO 0 (GPIO 1 on D0) is a valid GPIO with a mux bit number of zero, so add a high-bit on all valid entries to distinguish this from an uninitialised row in the table. Signed-off-by: Phil Elwell --- drivers/pinctrl/bcm/pinctrl-bcm2712.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) --- a/drivers/pinctrl/bcm/pinctrl-bcm2712.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2712.c @@ -60,22 +60,24 @@ }, \ } -#define REG_BIT_INVALID 0xffff +#define MUX_BIT_VALID 0x8000 +#define REG_BIT_INVALID 0xffff #define BIT_TO_REG(b) (((b) >> 5) << 2) #define BIT_TO_SHIFT(b) ((b) & 0x1f) +#define MUX_BIT(mr, mb) (MUX_BIT_VALID + ((mr)*4)*8 + (mb)*4) #define GPIO_REGS(n, mr, mb, pr, pb) \ - [n] = { ((mr)*4)*8 + (mb)*4, ((pr)*4)*8 + (pb)*2 } + [n] = { MUX_BIT(mr, mb), ((pr)*4)*8 + (pb)*2 } -#define EMMC_REGS(n, r, b) \ - [n] = { 0, ((r)*4)*8 + (b)*2 } +#define EMMC_REGS(n, pr, pb) \ + [n] = { 0, ((pr)*4)*8 + (pb)*2 } #define AGPIO_REGS(n, mr, mb, pr, pb) \ - [n] = { ((mr)*4)*8 + (mb)*4, ((pr)*4)*8 + (pb)*2 } + [n] = { MUX_BIT(mr, mb), ((pr)*4)*8 + (pb)*2 } #define SGPIO_REGS(n, mr, mb) \ - [n+32] = { ((mr)*4)*8 + (mb)*4, REG_BIT_INVALID } + [n+32] = { MUX_BIT(mr, mb), REG_BIT_INVALID } #define GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a) #define AGPIO_PIN(a) PINCTRL_PIN(a, "aon_gpio" #a) @@ -740,6 +742,7 @@ static enum bcm2712_funcs bcm2712_pinctr if (!bit) return func_gpio; + bit &= ~MUX_BIT_VALID; val = bcm2712_reg_rd(pc, BIT_TO_REG(bit)); fsel = (val >> BIT_TO_SHIFT(bit)) & BCM2712_FSEL_MASK; @@ -767,6 +770,7 @@ static void bcm2712_pinctrl_fsel_set( if (!bit || func >= func_count) return; + bit &= ~MUX_BIT_VALID; fsel = BCM2712_FSEL_COUNT;