From 0de9300833afc6b46d69c8d9584155a78c213f54 Mon Sep 17 00:00:00 2001 From: Dom Cobley Date: Tue, 6 Feb 2024 19:59:13 +0000 Subject: [PATCH 0885/1085] vc4/hvs: Support fixed alpha correctly on 2712D0 2712D0 removed alpha_mode from control word 2 for choosing fixed alpha and replaced it with the previously reserved value of 3 in alpha_mask. Handle this to fix corrupt desktop when using X on 2712D0 Signed-off-by: Dom Cobley --- drivers/gpu/drm/vc4/vc4_plane.c | 17 ++++++++++++++++- drivers/gpu/drm/vc4/vc4_regs.h | 3 +++ 2 files changed, 19 insertions(+), 1 deletion(-) --- a/drivers/gpu/drm/vc4/vc4_plane.c +++ b/drivers/gpu/drm/vc4/vc4_plane.c @@ -1079,6 +1079,21 @@ static u32 vc4_hvs5_get_alpha_blend_mode } } +static u32 vc4_hvs6_get_alpha_mask_mode(struct drm_plane_state *state) +{ + struct drm_device *dev = state->state->dev; + struct vc4_dev *vc4 = to_vc4_dev(dev); + + WARN_ON_ONCE(vc4->gen != VC4_GEN_6); + + if (vc4->step_d0 && (!state->fb->format->has_alpha || + state->pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE)) + return VC4_SET_FIELD(SCALER6_CTL0_ALPHA_MASK_FIXED, + SCALER6_CTL0_ALPHA_MASK); + + return VC4_SET_FIELD(SCALER6_CTL0_ALPHA_MASK_NONE, SCALER6_CTL0_ALPHA_MASK); +} + /* Writes out a full display list for an active plane to the plane's * private dlist state. */ @@ -1824,7 +1839,7 @@ static int vc6_plane_mode_set(struct drm vc4_dlist_write(vc4_state, SCALER6_CTL0_VALID | VC4_SET_FIELD(tiling, SCALER6_CTL0_ADDR_MODE) | - VC4_SET_FIELD(0, SCALER6_CTL0_ALPHA_MASK) | + vc4_hvs6_get_alpha_mask_mode(state) | (vc4_state->is_unity ? SCALER6_CTL0_UNITY : 0) | VC4_SET_FIELD(format->pixel_order_hvs5, SCALER6_CTL0_ORDERRGBA) | VC4_SET_FIELD(scl1, SCALER6_CTL0_SCL1_MODE) | --- a/drivers/gpu/drm/vc4/vc4_regs.h +++ b/drivers/gpu/drm/vc4/vc4_regs.h @@ -1408,6 +1408,9 @@ enum hvs_pixel_format { #define SCALER6_CTL0_ADDR_MODE_UIF 4 #define SCALER6_CTL0_ALPHA_MASK_MASK VC4_MASK(19, 18) +#define SCALER6_CTL0_ALPHA_MASK_NONE 0 +#define SCALER6_CTL0_ALPHA_MASK_FIXED 3 + #define SCALER6_CTL0_UNITY BIT(15) #define SCALER6_CTL0_ORDERRGBA_MASK VC4_MASK(14, 13) #define SCALER6_CTL0_SCL1_MODE_MASK VC4_MASK(10, 8)