;; Machine description for AArch64 architecture.
;; Copyright (C) 2009-2017 Free Software Foundation, Inc.
;; Contributed by ARM Ltd.
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify it
;; under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful, but
;; WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
;; General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; .
;; Register numbers
(define_constants
[
(R0_REGNUM 0)
(R1_REGNUM 1)
(R2_REGNUM 2)
(R3_REGNUM 3)
(R4_REGNUM 4)
(R5_REGNUM 5)
(R6_REGNUM 6)
(R7_REGNUM 7)
(R8_REGNUM 8)
(R9_REGNUM 9)
(R10_REGNUM 10)
(R11_REGNUM 11)
(R12_REGNUM 12)
(R13_REGNUM 13)
(R14_REGNUM 14)
(R15_REGNUM 15)
(R16_REGNUM 16)
(IP0_REGNUM 16)
(R17_REGNUM 17)
(IP1_REGNUM 17)
(R18_REGNUM 18)
(R19_REGNUM 19)
(R20_REGNUM 20)
(R21_REGNUM 21)
(R22_REGNUM 22)
(R23_REGNUM 23)
(R24_REGNUM 24)
(R25_REGNUM 25)
(R26_REGNUM 26)
(R27_REGNUM 27)
(R28_REGNUM 28)
(R29_REGNUM 29)
(R30_REGNUM 30)
(LR_REGNUM 30)
(SP_REGNUM 31)
(V0_REGNUM 32)
(V15_REGNUM 47)
(V31_REGNUM 63)
(LAST_SAVED_REGNUM 63)
(SFP_REGNUM 64)
(AP_REGNUM 65)
(CC_REGNUM 66)
]
)
(define_c_enum "unspec" [
UNSPEC_AUTI1716
UNSPEC_AUTISP
UNSPEC_CASESI
UNSPEC_CRC32B
UNSPEC_CRC32CB
UNSPEC_CRC32CH
UNSPEC_CRC32CW
UNSPEC_CRC32CX
UNSPEC_CRC32H
UNSPEC_CRC32W
UNSPEC_CRC32X
UNSPEC_FCVTZS
UNSPEC_FCVTZU
UNSPEC_URECPE
UNSPEC_FRECPE
UNSPEC_FRECPS
UNSPEC_FRECPX
UNSPEC_FRINTA
UNSPEC_FRINTI
UNSPEC_FRINTM
UNSPEC_FRINTN
UNSPEC_FRINTP
UNSPEC_FRINTX
UNSPEC_FRINTZ
UNSPEC_GOTSMALLPIC
UNSPEC_GOTSMALLPIC28K
UNSPEC_GOTSMALLTLS
UNSPEC_GOTTINYPIC
UNSPEC_GOTTINYTLS
UNSPEC_LD1
UNSPEC_LD2
UNSPEC_LD2_DUP
UNSPEC_LD3
UNSPEC_LD3_DUP
UNSPEC_LD4
UNSPEC_LD4_DUP
UNSPEC_LD2_LANE
UNSPEC_LD3_LANE
UNSPEC_LD4_LANE
UNSPEC_MB
UNSPEC_NOP
UNSPEC_PACI1716
UNSPEC_PACISP
UNSPEC_PRLG_STK
UNSPEC_RBIT
UNSPEC_SCVTF
UNSPEC_SISD_NEG
UNSPEC_SISD_SSHL
UNSPEC_SISD_USHL
UNSPEC_SSHL_2S
UNSPEC_ST1
UNSPEC_ST2
UNSPEC_ST3
UNSPEC_ST4
UNSPEC_ST2_LANE
UNSPEC_ST3_LANE
UNSPEC_ST4_LANE
UNSPEC_TLS
UNSPEC_TLSDESC
UNSPEC_TLSLE12
UNSPEC_TLSLE24
UNSPEC_TLSLE32
UNSPEC_TLSLE48
UNSPEC_UCVTF
UNSPEC_USHL_2S
UNSPEC_VSTRUCTDUMMY
UNSPEC_SP_SET
UNSPEC_SP_TEST
UNSPEC_RSQRT
UNSPEC_RSQRTE
UNSPEC_RSQRTS
UNSPEC_NZCV
UNSPEC_XPACLRI
UNSPEC_COPYSIGN
])
(define_c_enum "unspecv" [
UNSPECV_EH_RETURN ; Represent EH_RETURN
UNSPECV_GET_FPCR ; Represent fetch of FPCR content.
UNSPECV_SET_FPCR ; Represent assign of FPCR content.
UNSPECV_GET_FPSR ; Represent fetch of FPSR content.
UNSPECV_SET_FPSR ; Represent assign of FPSR content.
UNSPECV_BLOCKAGE ; Represent a blockage
UNSPECV_PROBE_STACK_RANGE ; Represent stack range probing.
]
)
;; If further include files are added the defintion of MD_INCLUDES
;; must be updated.
(include "constraints.md")
(include "predicates.md")
(include "iterators.md")
;; -------------------------------------------------------------------
;; Instruction types and attributes
;; -------------------------------------------------------------------
; The "type" attribute is included here from AArch32 backend to be able
; to share pipeline descriptions.
(include "../arm/types.md")
;; It is important to set the fp or simd attributes to yes when a pattern
;; alternative uses the FP or SIMD register files, usually signified by use of
;; the 'w' constraint. This will ensure that the alternative will be
;; disabled when compiling with -mgeneral-regs-only or with the +nofp/+nosimd
;; architecture extensions. If all the alternatives in a pattern use the
;; FP or SIMD registers then the pattern predicate should include TARGET_FLOAT
;; or TARGET_SIMD.
;; Attribute that specifies whether or not the instruction touches fp
;; registers. When this is set to yes for an alternative, that alternative
;; will be disabled when !TARGET_FLOAT.
(define_attr "fp" "no,yes" (const_string "no"))
;; Attribute that specifies whether or not the instruction touches simd
;; registers. When this is set to yes for an alternative, that alternative
;; will be disabled when !TARGET_SIMD.
(define_attr "simd" "no,yes" (const_string "no"))
(define_attr "length" ""
(const_int 4))
;; Attribute that controls whether an alternative is enabled or not.
;; Currently it is only used to disable alternatives which touch fp or simd
;; registers when -mgeneral-regs-only is specified.
(define_attr "enabled" "no,yes"
(cond [(ior
(and (eq_attr "fp" "yes")
(eq (symbol_ref "TARGET_FLOAT") (const_int 0)))
(and (eq_attr "simd" "yes")
(eq (symbol_ref "TARGET_SIMD") (const_int 0))))
(const_string "no")
] (const_string "yes")))
;; Attribute that specifies whether we are dealing with a branch to a
;; label that is far away, i.e. further away than the maximum/minimum
;; representable in a signed 21-bits number.
;; 0 :=: no
;; 1 :=: yes
(define_attr "far_branch" "" (const_int 0))
;; Strictly for compatibility with AArch32 in pipeline models, since AArch64 has
;; no predicated insns.
(define_attr "predicated" "yes,no" (const_string "no"))
;; -------------------------------------------------------------------
;; Pipeline descriptions and scheduling
;; -------------------------------------------------------------------
;; Processor types.
(include "aarch64-tune.md")
;; Scheduling
(include "../arm/cortex-a53.md")
(include "../arm/cortex-a57.md")
(include "../arm/exynos-m1.md")
(include "thunderx.md")
(include "../arm/xgene1.md")
(include "thunderx2t99.md")
;; -------------------------------------------------------------------
;; Jumps and other miscellaneous insns
;; -------------------------------------------------------------------
(define_insn "indirect_jump"
[(set (pc) (match_operand:DI 0 "register_operand" "r"))]
""
"br\\t%0"
[(set_attr "type" "branch")]
)
(define_insn "jump"
[(set (pc) (label_ref (match_operand 0 "" "")))]
""
"b\\t%l0"
[(set_attr "type" "branch")]
)
(define_expand "cbranch4"
[(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
[(match_operand:GPI 1 "register_operand" "")
(match_operand:GPI 2 "aarch64_plus_operand" "")])
(label_ref (match_operand 3 "" ""))
(pc)))]
""
"
operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1],
operands[2]);
operands[2] = const0_rtx;
"
)
(define_expand "cbranch4"
[(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
[(match_operand:GPF 1 "register_operand" "")
(match_operand:GPF 2 "aarch64_fp_compare_operand" "")])
(label_ref (match_operand 3 "" ""))
(pc)))]
""
"
operands[1] = aarch64_gen_compare_reg (GET_CODE (operands[0]), operands[1],
operands[2]);
operands[2] = const0_rtx;
"
)
(define_expand "cbranchcc4"
[(set (pc) (if_then_else
(match_operator 0 "aarch64_comparison_operator"
[(match_operand 1 "cc_register" "")
(match_operand 2 "const0_operand")])
(label_ref (match_operand 3 "" ""))
(pc)))]
""
"")
(define_insn "ccmp"
[(set (match_operand:CC 1 "cc_register" "")
(if_then_else:CC
(match_operator 4 "aarch64_comparison_operator"
[(match_operand 0 "cc_register" "")
(const_int 0)])
(compare:CC
(match_operand:GPI 2 "register_operand" "r,r,r")
(match_operand:GPI 3 "aarch64_ccmp_operand" "r,Uss,Usn"))
(unspec:CC [(match_operand 5 "immediate_operand")] UNSPEC_NZCV)))]
""
"@
ccmp\\t%2, %3, %k5, %m4
ccmp\\t%2, %3, %k5, %m4
ccmn\\t%2, #%n3, %k5, %m4"
[(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
)
(define_insn "fccmp"
[(set (match_operand:CCFP 1 "cc_register" "")
(if_then_else:CCFP
(match_operator 4 "aarch64_comparison_operator"
[(match_operand 0 "cc_register" "")
(const_int 0)])
(compare:CCFP
(match_operand:GPF 2 "register_operand" "w")
(match_operand:GPF 3 "register_operand" "w"))
(unspec:CCFP [(match_operand 5 "immediate_operand")] UNSPEC_NZCV)))]
"TARGET_FLOAT"
"fccmp\\t%2, %3, %k5, %m4"
[(set_attr "type" "fccmp")]
)
(define_insn "fccmpe"
[(set (match_operand:CCFPE 1 "cc_register" "")
(if_then_else:CCFPE
(match_operator 4 "aarch64_comparison_operator"
[(match_operand 0 "cc_register" "")
(const_int 0)])
(compare:CCFPE
(match_operand:GPF 2 "register_operand" "w")
(match_operand:GPF 3 "register_operand" "w"))
(unspec:CCFPE [(match_operand 5 "immediate_operand")] UNSPEC_NZCV)))]
"TARGET_FLOAT"
"fccmpe\\t%2, %3, %k5, %m4"
[(set_attr "type" "fccmp")]
)
;; Expansion of signed mod by a power of 2 using CSNEG.
;; For x0 % n where n is a power of 2 produce:
;; negs x1, x0
;; and x0, x0, #(n - 1)
;; and x1, x1, #(n - 1)
;; csneg x0, x0, x1, mi
(define_expand "mod3"
[(match_operand:GPI 0 "register_operand" "")
(match_operand:GPI 1 "register_operand" "")
(match_operand:GPI 2 "const_int_operand" "")]
""
{
HOST_WIDE_INT val = INTVAL (operands[2]);
if (val <= 0
|| exact_log2 (val) <= 0
|| !aarch64_bitmask_imm (val - 1, mode))
FAIL;
rtx mask = GEN_INT (val - 1);
/* In the special case of x0 % 2 we can do the even shorter:
cmp x0, xzr
and x0, x0, 1
cneg x0, x0, lt. */
if (val == 2)
{
rtx masked = gen_reg_rtx (mode);
rtx ccreg = aarch64_gen_compare_reg (LT, operands[1], const0_rtx);
emit_insn (gen_and3 (masked, operands[1], mask));
rtx x = gen_rtx_LT (VOIDmode, ccreg, const0_rtx);
emit_insn (gen_csneg3_insn (operands[0], x, masked, masked));
DONE;
}
rtx neg_op = gen_reg_rtx (mode);
rtx_insn *insn = emit_insn (gen_neg2_compare0 (neg_op, operands[1]));
/* Extract the condition register and mode. */
rtx cmp = XVECEXP (PATTERN (insn), 0, 0);
rtx cc_reg = SET_DEST (cmp);
rtx cond = gen_rtx_GE (VOIDmode, cc_reg, const0_rtx);
rtx masked_pos = gen_reg_rtx (mode);
emit_insn (gen_and3 (masked_pos, operands[1], mask));
rtx masked_neg = gen_reg_rtx (mode);
emit_insn (gen_and3 (masked_neg, neg_op, mask));
emit_insn (gen_csneg3_insn (operands[0], cond,
masked_neg, masked_pos));
DONE;
}
)
(define_insn "condjump"
[(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
[(match_operand 1 "cc_register" "") (const_int 0)])
(label_ref (match_operand 2 "" ""))
(pc)))]
""
{
if (get_attr_length (insn) == 8)
return aarch64_gen_far_branch (operands, 2, "Lbcond", "b%M0\\t");
else
return "b%m0\\t%l2";
}
[(set_attr "type" "branch")
(set (attr "length")
(if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -1048576))
(lt (minus (match_dup 2) (pc)) (const_int 1048572)))
(const_int 4)
(const_int 8)))
(set (attr "far_branch")
(if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -1048576))
(lt (minus (match_dup 2) (pc)) (const_int 1048572)))
(const_int 0)
(const_int 1)))]
)
;; For a 24-bit immediate CST we can optimize the compare for equality
;; and branch sequence from:
;; mov x0, #imm1
;; movk x0, #imm2, lsl 16 /* x0 contains CST. */
;; cmp x1, x0
;; b .Label
;; into the shorter:
;; sub x0, x1, #(CST & 0xfff000)
;; subs x0, x0, #(CST & 0x000fff)
;; b .Label
(define_insn_and_split "*compare_condjump"
[(set (pc) (if_then_else (EQL
(match_operand:GPI 0 "register_operand" "r")
(match_operand:GPI 1 "aarch64_imm24" "n"))
(label_ref:P (match_operand 2 "" ""))
(pc)))]
"!aarch64_move_imm (INTVAL (operands[1]), mode)
&& !aarch64_plus_operand (operands[1], mode)
&& !reload_completed"
"#"
"&& true"
[(const_int 0)]
{
HOST_WIDE_INT lo_imm = UINTVAL (operands[1]) & 0xfff;
HOST_WIDE_INT hi_imm = UINTVAL (operands[1]) & 0xfff000;
rtx tmp = gen_reg_rtx (mode);
emit_insn (gen_add3 (tmp, operands[0], GEN_INT (-hi_imm)));
emit_insn (gen_add3_compare0 (tmp, tmp, GEN_INT (-lo_imm)));
rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM);
rtx cmp_rtx = gen_rtx_fmt_ee (, mode, cc_reg, const0_rtx);
emit_jump_insn (gen_condjump (cmp_rtx, cc_reg, operands[2]));
DONE;
}
)
(define_expand "casesi"
[(match_operand:SI 0 "register_operand" "") ; Index
(match_operand:SI 1 "const_int_operand" "") ; Lower bound
(match_operand:SI 2 "const_int_operand" "") ; Total range
(match_operand:DI 3 "" "") ; Table label
(match_operand:DI 4 "" "")] ; Out of range label
""
{
if (operands[1] != const0_rtx)
{
rtx reg = gen_reg_rtx (SImode);
/* Canonical RTL says that if you have:
(minus (X) (CONST))
then this should be emitted as:
(plus (X) (-CONST))
The use of trunc_int_for_mode ensures that the resulting
constant can be represented in SImode, this is important
for the corner case where operand[1] is INT_MIN. */
operands[1] = GEN_INT (trunc_int_for_mode (-INTVAL (operands[1]), SImode));
if (!(*insn_data[CODE_FOR_addsi3].operand[2].predicate)
(operands[1], SImode))
operands[1] = force_reg (SImode, operands[1]);
emit_insn (gen_addsi3 (reg, operands[0], operands[1]));
operands[0] = reg;
}
if (!aarch64_plus_operand (operands[2], SImode))
operands[2] = force_reg (SImode, operands[2]);
emit_jump_insn (gen_cbranchsi4 (gen_rtx_GTU (SImode, const0_rtx,
const0_rtx),
operands[0], operands[2], operands[4]));
operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (VOIDmode, operands[3]));
emit_jump_insn (gen_casesi_dispatch (operands[2], operands[0],
operands[3]));
DONE;
}
)
(define_insn "casesi_dispatch"
[(parallel
[(set (pc)
(mem:DI (unspec [(match_operand:DI 0 "register_operand" "r")
(match_operand:SI 1 "register_operand" "r")]
UNSPEC_CASESI)))
(clobber (reg:CC CC_REGNUM))
(clobber (match_scratch:DI 3 "=r"))
(clobber (match_scratch:DI 4 "=r"))
(use (label_ref (match_operand 2 "" "")))])]
""
"*
return aarch64_output_casesi (operands);
"
[(set_attr "length" "16")
(set_attr "type" "branch")]
)
(define_insn "nop"
[(unspec[(const_int 0)] UNSPEC_NOP)]
""
"nop"
[(set_attr "type" "no_insn")]
)
(define_insn "prefetch"
[(prefetch (match_operand:DI 0 "register_operand" "r")
(match_operand:QI 1 "const_int_operand" "")
(match_operand:QI 2 "const_int_operand" ""))]
""
{
const char * pftype[2][4] =
{
{"prfm\\tPLDL1STRM, %a0",
"prfm\\tPLDL3KEEP, %a0",
"prfm\\tPLDL2KEEP, %a0",
"prfm\\tPLDL1KEEP, %a0"},
{"prfm\\tPSTL1STRM, %a0",
"prfm\\tPSTL3KEEP, %a0",
"prfm\\tPSTL2KEEP, %a0",
"prfm\\tPSTL1KEEP, %a0"},
};
int locality = INTVAL (operands[2]);
gcc_assert (IN_RANGE (locality, 0, 3));
return pftype[INTVAL(operands[1])][locality];
}
[(set_attr "type" "load1")]
)
(define_insn "trap"
[(trap_if (const_int 1) (const_int 8))]
""
"brk #1000"
[(set_attr "type" "trap")])
(define_expand "prologue"
[(clobber (const_int 0))]
""
"
aarch64_expand_prologue ();
DONE;
"
)
(define_expand "epilogue"
[(clobber (const_int 0))]
""
"
aarch64_expand_epilogue (false);
DONE;
"
)
(define_expand "sibcall_epilogue"
[(clobber (const_int 0))]
""
"
aarch64_expand_epilogue (true);
DONE;
"
)
(define_insn "*do_return"
[(return)]
""
{
if (aarch64_return_address_signing_enabled ()
&& TARGET_ARMV8_3
&& !crtl->calls_eh_return)
return "retaa";
return "ret";
}
[(set_attr "type" "branch")]
)
(define_expand "return"
[(simple_return)]
"aarch64_use_return_insn_p ()"
""
)
(define_insn "simple_return"
[(simple_return)]
""
"ret"
[(set_attr "type" "branch")]
)
(define_insn "*cb1"
[(set (pc) (if_then_else (EQL (match_operand:GPI 0 "register_operand" "r")
(const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))]
""
{
if (get_attr_length (insn) == 8)
return aarch64_gen_far_branch (operands, 1, "Lcb", "\\t%0, ");
else
return "\\t%0, %l1";
}
[(set_attr "type" "branch")
(set (attr "length")
(if_then_else (and (ge (minus (match_dup 1) (pc)) (const_int -1048576))
(lt (minus (match_dup 1) (pc)) (const_int 1048572)))
(const_int 4)
(const_int 8)))
(set (attr "far_branch")
(if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -1048576))
(lt (minus (match_dup 2) (pc)) (const_int 1048572)))
(const_int 0)
(const_int 1)))]
)
(define_insn "*tb1"
[(set (pc) (if_then_else
(EQL (zero_extract:DI (match_operand:GPI 0 "register_operand" "r")
(const_int 1)
(match_operand 1
"aarch64_simd_shift_imm_" "n"))
(const_int 0))
(label_ref (match_operand 2 "" ""))
(pc)))
(clobber (reg:CC CC_REGNUM))]
""
{
if (get_attr_length (insn) == 8)
{
if (get_attr_far_branch (insn) == 1)
return aarch64_gen_far_branch (operands, 2, "Ltb",
"\\t%0, %1, ");
else
{
operands[1] = GEN_INT (HOST_WIDE_INT_1U << UINTVAL (operands[1]));
return "tst\t%0, %1\;\t%l2";
}
}
else
return "\t%0, %1, %l2";
}
[(set_attr "type" "branch")
(set (attr "length")
(if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
(lt (minus (match_dup 2) (pc)) (const_int 32764)))
(const_int 4)
(const_int 8)))
(set (attr "far_branch")
(if_then_else (and (ge (minus (match_dup 2) (pc)) (const_int -1048576))
(lt (minus (match_dup 2) (pc)) (const_int 1048572)))
(const_int 0)
(const_int 1)))]
)
(define_insn "*cb1"
[(set (pc) (if_then_else (LTGE (match_operand:ALLI 0 "register_operand" "r")
(const_int 0))
(label_ref (match_operand 1 "" ""))
(pc)))
(clobber (reg:CC CC_REGNUM))]
""
{
if (get_attr_length (insn) == 8)
{
if (get_attr_far_branch (insn) == 1)
return aarch64_gen_far_branch (operands, 1, "Ltb",
"\\t%0, , ");
else
{
char buf[64];
uint64_t val = ((uint64_t) 1)
<< (GET_MODE_SIZE (mode) * BITS_PER_UNIT - 1);
sprintf (buf, "tst\t%%0, %" PRId64, val);
output_asm_insn (buf, operands);
return "\t%l1";
}
}
else
return "\t%0, , %l1";
}
[(set_attr "type" "branch")
(set (attr "length")
(if_then_else (and (ge (minus (match_dup 1) (pc)) (const_int -32768))
(lt (minus (match_dup 1) (pc)) (const_int 32764)))
(const_int 4)
(const_int 8)))
(set (attr "far_branch")
(if_then_else (and (ge (minus (match_dup 1) (pc)) (const_int -1048576))
(lt (minus (match_dup 1) (pc)) (const_int 1048572)))
(const_int 0)
(const_int 1)))]
)
;; -------------------------------------------------------------------
;; Subroutine calls and sibcalls
;; -------------------------------------------------------------------
(define_expand "call_internal"
[(parallel [(call (match_operand 0 "memory_operand" "")
(match_operand 1 "general_operand" ""))
(use (match_operand 2 "" ""))
(clobber (reg:DI LR_REGNUM))])])
(define_expand "call"
[(parallel [(call (match_operand 0 "memory_operand" "")
(match_operand 1 "general_operand" ""))
(use (match_operand 2 "" ""))
(clobber (reg:DI LR_REGNUM))])]
""
"
{
rtx callee, pat;
/* In an untyped call, we can get NULL for operand 2. */
if (operands[2] == NULL)
operands[2] = const0_rtx;
/* Decide if we should generate indirect calls by loading the
64-bit address of the callee into a register before performing
the branch-and-link. */
callee = XEXP (operands[0], 0);
if (GET_CODE (callee) == SYMBOL_REF
? (aarch64_is_long_call_p (callee)
|| aarch64_is_noplt_call_p (callee))
: !REG_P (callee))
XEXP (operands[0], 0) = force_reg (Pmode, callee);
pat = gen_call_internal (operands[0], operands[1], operands[2]);
aarch64_emit_call_insn (pat);
DONE;
}"
)
(define_insn "*call_reg"
[(call (mem:DI (match_operand:DI 0 "register_operand" "r"))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
(clobber (reg:DI LR_REGNUM))]
""
"blr\\t%0"
[(set_attr "type" "call")]
)
(define_insn "*call_symbol"
[(call (mem:DI (match_operand:DI 0 "" ""))
(match_operand 1 "" ""))
(use (match_operand 2 "" ""))
(clobber (reg:DI LR_REGNUM))]
"GET_CODE (operands[0]) == SYMBOL_REF
&& !aarch64_is_long_call_p (operands[0])
&& !aarch64_is_noplt_call_p (operands[0])"
"bl\\t%a0"
[(set_attr "type" "call")]
)
(define_expand "call_value_internal"
[(parallel [(set (match_operand 0 "" "")
(call (match_operand 1 "memory_operand" "")
(match_operand 2 "general_operand" "")))
(use (match_operand 3 "" ""))
(clobber (reg:DI LR_REGNUM))])])
(define_expand "call_value"
[(parallel [(set (match_operand 0 "" "")
(call (match_operand 1 "memory_operand" "")
(match_operand 2 "general_operand" "")))
(use (match_operand 3 "" ""))
(clobber (reg:DI LR_REGNUM))])]
""
"
{
rtx callee, pat;
/* In an untyped call, we can get NULL for operand 3. */
if (operands[3] == NULL)
operands[3] = const0_rtx;
/* Decide if we should generate indirect calls by loading the
64-bit address of the callee into a register before performing
the branch-and-link. */
callee = XEXP (operands[1], 0);
if (GET_CODE (callee) == SYMBOL_REF
? (aarch64_is_long_call_p (callee)
|| aarch64_is_noplt_call_p (callee))
: !REG_P (callee))
XEXP (operands[1], 0) = force_reg (Pmode, callee);
pat = gen_call_value_internal (operands[0], operands[1], operands[2],
operands[3]);
aarch64_emit_call_insn (pat);
DONE;
}"
)
(define_insn "*call_value_reg"
[(set (match_operand 0 "" "")
(call (mem:DI (match_operand:DI 1 "register_operand" "r"))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
(clobber (reg:DI LR_REGNUM))]
""
"blr\\t%1"
[(set_attr "type" "call")]
)
(define_insn "*call_value_symbol"
[(set (match_operand 0 "" "")
(call (mem:DI (match_operand:DI 1 "" ""))
(match_operand 2 "" "")))
(use (match_operand 3 "" ""))
(clobber (reg:DI LR_REGNUM))]
"GET_CODE (operands[1]) == SYMBOL_REF
&& !aarch64_is_long_call_p (operands[1])
&& !aarch64_is_noplt_call_p (operands[1])"
"bl\\t%a1"
[(set_attr "type" "call")]
)
(define_expand "sibcall_internal"
[(parallel [(call (match_operand 0 "memory_operand" "")
(match_operand 1 "general_operand" ""))
(return)
(use (match_operand 2 "" ""))])])
(define_expand "sibcall"
[(parallel [(call (match_operand 0 "memory_operand" "")
(match_operand 1 "general_operand" ""))
(return)
(use (match_operand 2 "" ""))])]
""
{
rtx pat;
rtx callee = XEXP (operands[0], 0);
if (!REG_P (callee)
&& ((GET_CODE (callee) != SYMBOL_REF)
|| aarch64_is_noplt_call_p (callee)))
XEXP (operands[0], 0) = force_reg (Pmode, callee);
if (operands[2] == NULL_RTX)
operands[2] = const0_rtx;
pat = gen_sibcall_internal (operands[0], operands[1], operands[2]);
aarch64_emit_call_insn (pat);
DONE;
}
)
(define_expand "sibcall_value_internal"
[(parallel [(set (match_operand 0 "" "")
(call (match_operand 1 "memory_operand" "")
(match_operand 2 "general_operand" "")))
(return)
(use (match_operand 3 "" ""))])])
(define_expand "sibcall_value"
[(parallel [(set (match_operand 0 "" "")
(call (match_operand 1 "memory_operand" "")
(match_operand 2 "general_operand" "")))
(return)
(use (match_operand 3 "" ""))])]
""
{
rtx pat;
rtx callee = XEXP (operands[1], 0);
if (!REG_P (callee)
&& ((GET_CODE (callee) != SYMBOL_REF)
|| aarch64_is_noplt_call_p (callee)))
XEXP (operands[1], 0) = force_reg (Pmode, callee);
if (operands[3] == NULL_RTX)
operands[3] = const0_rtx;
pat = gen_sibcall_value_internal (operands[0], operands[1], operands[2],
operands[3]);
aarch64_emit_call_insn (pat);
DONE;
}
)
(define_insn "*sibcall_insn"
[(call (mem:DI (match_operand:DI 0 "aarch64_call_insn_operand" "Ucs, Usf"))
(match_operand 1 "" ""))
(return)
(use (match_operand 2 "" ""))]
"SIBLING_CALL_P (insn)"
"@
br\\t%0
b\\t%a0"
[(set_attr "type" "branch, branch")]
)
(define_insn "*sibcall_value_insn"
[(set (match_operand 0 "" "")
(call (mem:DI
(match_operand:DI 1 "aarch64_call_insn_operand" "Ucs, Usf"))
(match_operand 2 "" "")))
(return)
(use (match_operand 3 "" ""))]
"SIBLING_CALL_P (insn)"
"@
br\\t%1
b\\t%a1"
[(set_attr "type" "branch, branch")]
)
;; Call subroutine returning any type.
(define_expand "untyped_call"
[(parallel [(call (match_operand 0 "")
(const_int 0))
(match_operand 1 "")
(match_operand 2 "")])]
""
{
int i;
emit_call_insn (gen_call (operands[0], const0_rtx, NULL));
for (i = 0; i < XVECLEN (operands[2], 0); i++)
{
rtx set = XVECEXP (operands[2], 0, i);
emit_move_insn (SET_DEST (set), SET_SRC (set));
}
/* The optimizer does not know that the call sets the function value
registers we stored in the result block. We avoid problems by
claiming that all hard registers are used and clobbered at this
point. */
emit_insn (gen_blockage ());
DONE;
})
;; -------------------------------------------------------------------
;; Moves
;; -------------------------------------------------------------------
(define_expand "mov"
[(set (match_operand:SHORT 0 "nonimmediate_operand" "")
(match_operand:SHORT 1 "general_operand" ""))]
""
"
if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
operands[1] = force_reg (mode, operands[1]);
"
)
(define_insn "*mov_aarch64"
[(set (match_operand:SHORT 0 "nonimmediate_operand" "=r,r, *w,r,*w, m, m, r,*w,*w")
(match_operand:SHORT 1 "general_operand" " r,M,D,m, m,rZ,*w,*w, r,*w"))]
"(register_operand (operands[0], mode)
|| aarch64_reg_or_zero (operands[1], mode))"
{
switch (which_alternative)
{
case 0:
return "mov\t%w0, %w1";
case 1:
return "mov\t%w0, %1";
case 2:
return aarch64_output_scalar_simd_mov_immediate (operands[1],
mode);
case 3:
return "ldr\t%w0, %1";
case 4:
return "ldr\t%0, %1";
case 5:
return "str\t%w1, %0";
case 6:
return "str\t%1, %0";
case 7:
return "umov\t%w0, %1.[0]";
case 8:
return "dup\t%0., %w1";
case 9:
return "dup\t%0, %1.[0]";
default:
gcc_unreachable ();
}
}
[(set_attr "type" "mov_reg,mov_imm,neon_move,load1,load1,store1,store1,\
neon_to_gp,neon_from_gp,neon_dup")
(set_attr "simd" "*,*,yes,*,*,*,*,yes,yes,yes")]
)
(define_expand "mov"
[(set (match_operand:GPI 0 "nonimmediate_operand" "")
(match_operand:GPI 1 "general_operand" ""))]
""
"
if (MEM_P (operands[0]) && CONST_INT_P (operands[1])
&& mode == DImode
&& aarch64_split_dimode_const_store (operands[0], operands[1]))
DONE;
if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
operands[1] = force_reg (mode, operands[1]);
/* FIXME: RR we still need to fix up what we are doing with
symbol_refs and other types of constants. */
if (CONSTANT_P (operands[1])
&& !CONST_INT_P (operands[1]))
{
aarch64_expand_mov_immediate (operands[0], operands[1]);
DONE;
}
"
)
(define_insn_and_split "*movsi_aarch64"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,k,r,r,r,r,*w,m, m,r,r ,*w, r,*w")
(match_operand:SI 1 "aarch64_mov_operand" " r,r,k,M,n,m, m,rZ,*w,S,Ush,rZ,*w,*w"))]
"(register_operand (operands[0], SImode)
|| aarch64_reg_or_zero (operands[1], SImode))"
"@
mov\\t%w0, %w1
mov\\t%w0, %w1
mov\\t%w0, %w1
mov\\t%w0, %1
#
ldr\\t%w0, %1
ldr\\t%s0, %1
str\\t%w1, %0
str\\t%s1, %0
adr\\t%x0, %a1
adrp\\t%x0, %A1
fmov\\t%s0, %w1
fmov\\t%w0, %s1
fmov\\t%s0, %s1"
"CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), SImode)
&& REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))"
[(const_int 0)]
"{
aarch64_expand_mov_immediate (operands[0], operands[1]);
DONE;
}"
[(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\
adr,adr,f_mcr,f_mrc,fmov")
(set_attr "fp" "*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes")]
)
(define_insn_and_split "*movdi_aarch64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,k,r,r,r,r,*w,m, m,r,r, *w, r,*w,w")
(match_operand:DI 1 "aarch64_mov_operand" " r,r,k,N,n,m, m,rZ,*w,S,Ush,rZ,*w,*w,Dd"))]
"(register_operand (operands[0], DImode)
|| aarch64_reg_or_zero (operands[1], DImode))"
"@
mov\\t%x0, %x1
mov\\t%0, %x1
mov\\t%x0, %1
mov\\t%x0, %1
#
ldr\\t%x0, %1
ldr\\t%d0, %1
str\\t%x1, %0
str\\t%d1, %0
adr\\t%x0, %a1
adrp\\t%x0, %A1
fmov\\t%d0, %x1
fmov\\t%x0, %d1
fmov\\t%d0, %d1
movi\\t%d0, %1"
"(CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), DImode))
&& REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))"
[(const_int 0)]
"{
aarch64_expand_mov_immediate (operands[0], operands[1]);
DONE;
}"
[(set_attr "type" "mov_reg,mov_reg,mov_reg,mov_imm,mov_imm,load1,load1,store1,store1,\
adr,adr,f_mcr,f_mrc,fmov,neon_move")
(set_attr "fp" "*,*,*,*,*,*,yes,*,yes,*,*,yes,yes,yes,*")
(set_attr "simd" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes")]
)
(define_insn "insv_imm"
[(set (zero_extract:GPI (match_operand:GPI 0 "register_operand" "+r")
(const_int 16)
(match_operand:GPI 1 "const_int_operand" "n"))
(match_operand:GPI 2 "const_int_operand" "n"))]
"UINTVAL (operands[1]) < GET_MODE_BITSIZE (mode)
&& UINTVAL (operands[1]) % 16 == 0"
"movk\\t%0, %X2, lsl %1"
[(set_attr "type" "mov_imm")]
)
(define_expand "movti"
[(set (match_operand:TI 0 "nonimmediate_operand" "")
(match_operand:TI 1 "general_operand" ""))]
""
"
if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
operands[1] = force_reg (TImode, operands[1]);
"
)
(define_insn "*movti_aarch64"
[(set (match_operand:TI 0
"nonimmediate_operand" "=r, *w,r ,*w,r,m,m,*w,m")
(match_operand:TI 1
"aarch64_movti_operand" " rn,r ,*w,*w,m,r,Z, m,*w"))]
"(register_operand (operands[0], TImode)
|| aarch64_reg_or_zero (operands[1], TImode))"
"@
#
#
#
orr\\t%0.16b, %1.16b, %1.16b
ldp\\t%0, %H0, %1
stp\\t%1, %H1, %0
stp\\txzr, xzr, %0
ldr\\t%q0, %1
str\\t%q1, %0"
[(set_attr "type" "multiple,f_mcr,f_mrc,neon_logic_q, \
load2,store2,store2,f_loadd,f_stored")
(set_attr "length" "8,8,8,4,4,4,4,4,4")
(set_attr "simd" "*,*,*,yes,*,*,*,*,*")
(set_attr "fp" "*,*,*,*,*,*,*,yes,yes")]
)
;; Split a TImode register-register or register-immediate move into
;; its component DImode pieces, taking care to handle overlapping
;; source and dest registers.
(define_split
[(set (match_operand:TI 0 "register_operand" "")
(match_operand:TI 1 "aarch64_reg_or_imm" ""))]
"reload_completed && aarch64_split_128bit_move_p (operands[0], operands[1])"
[(const_int 0)]
{
aarch64_split_128bit_move (operands[0], operands[1]);
DONE;
})
(define_expand "mov"
[(set (match_operand:GPF_TF_F16 0 "nonimmediate_operand" "")
(match_operand:GPF_TF_F16 1 "general_operand" ""))]
""
{
if (!TARGET_FLOAT)
{
aarch64_err_no_fpadvsimd (mode, "code");
FAIL;
}
if (GET_CODE (operands[0]) == MEM
&& ! (GET_CODE (operands[1]) == CONST_DOUBLE
&& aarch64_float_const_zero_rtx_p (operands[1])))
operands[1] = force_reg (mode, operands[1]);
}
)
(define_insn "*movhf_aarch64"
[(set (match_operand:HF 0 "nonimmediate_operand" "=w,w ,?r,w,w,m,r,m ,r")
(match_operand:HF 1 "general_operand" "Y ,?rY, w,w,m,w,m,rY,r"))]
"TARGET_FLOAT && (register_operand (operands[0], HFmode)
|| aarch64_reg_or_fp_zero (operands[1], HFmode))"
"@
movi\\t%0.4h, #0
mov\\t%0.h[0], %w1
umov\\t%w0, %1.h[0]
mov\\t%0.h[0], %1.h[0]
ldr\\t%h0, %1
str\\t%h1, %0
ldrh\\t%w0, %1
strh\\t%w1, %0
mov\\t%w0, %w1"
[(set_attr "type" "neon_move,neon_from_gp,neon_to_gp,neon_move,\
f_loads,f_stores,load1,store1,mov_reg")
(set_attr "simd" "yes,yes,yes,yes,*,*,*,*,*")]
)
(define_insn "*movsf_aarch64"
[(set (match_operand:SF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w,m,r,m ,r")
(match_operand:SF 1 "general_operand" "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))]
"TARGET_FLOAT && (register_operand (operands[0], SFmode)
|| aarch64_reg_or_fp_zero (operands[1], SFmode))"
"@
movi\\t%0.2s, #0
fmov\\t%s0, %w1
fmov\\t%w0, %s1
fmov\\t%s0, %s1
fmov\\t%s0, %1
ldr\\t%s0, %1
str\\t%s1, %0
ldr\\t%w0, %1
str\\t%w1, %0
mov\\t%w0, %w1"
[(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconsts,\
f_loads,f_stores,load1,store1,mov_reg")
(set_attr "simd" "yes,*,*,*,*,*,*,*,*,*")]
)
(define_insn "*movdf_aarch64"
[(set (match_operand:DF 0 "nonimmediate_operand" "=w,w ,?r,w,w ,w,m,r,m ,r")
(match_operand:DF 1 "general_operand" "Y ,?rY, w,w,Ufc,m,w,m,rY,r"))]
"TARGET_FLOAT && (register_operand (operands[0], DFmode)
|| aarch64_reg_or_fp_zero (operands[1], DFmode))"
"@
movi\\t%d0, #0
fmov\\t%d0, %x1
fmov\\t%x0, %d1
fmov\\t%d0, %d1
fmov\\t%d0, %1
ldr\\t%d0, %1
str\\t%d1, %0
ldr\\t%x0, %1
str\\t%x1, %0
mov\\t%x0, %x1"
[(set_attr "type" "neon_move,f_mcr,f_mrc,fmov,fconstd,\
f_loadd,f_stored,load1,store1,mov_reg")
(set_attr "simd" "yes,*,*,*,*,*,*,*,*,*")]
)
(define_insn "*movtf_aarch64"
[(set (match_operand:TF 0
"nonimmediate_operand" "=w,?&r,w ,?r,w,?w,w,m,?r,m ,m")
(match_operand:TF 1
"general_operand" " w,?r, ?r,w ,Y,Y ,m,w,m ,?r,Y"))]
"TARGET_FLOAT && (register_operand (operands[0], TFmode)
|| aarch64_reg_or_fp_zero (operands[1], TFmode))"
"@
orr\\t%0.16b, %1.16b, %1.16b
#
#
#
movi\\t%0.2d, #0
fmov\\t%s0, wzr
ldr\\t%q0, %1
str\\t%q1, %0
ldp\\t%0, %H0, %1
stp\\t%1, %H1, %0
stp\\txzr, xzr, %0"
[(set_attr "type" "logic_reg,multiple,f_mcr,f_mrc,neon_move_q,f_mcr,\
f_loadd,f_stored,load2,store2,store2")
(set_attr "length" "4,8,8,8,4,4,4,4,4,4,4")
(set_attr "simd" "yes,*,*,*,yes,*,*,*,*,*,*")]
)
(define_split
[(set (match_operand:TF 0 "register_operand" "")
(match_operand:TF 1 "aarch64_reg_or_imm" ""))]
"reload_completed && aarch64_split_128bit_move_p (operands[0], operands[1])"
[(const_int 0)]
{
aarch64_split_128bit_move (operands[0], operands[1]);
DONE;
}
)
;; 0 is dst
;; 1 is src
;; 2 is size of move in bytes
;; 3 is alignment
(define_expand "movmemdi"
[(match_operand:BLK 0 "memory_operand")
(match_operand:BLK 1 "memory_operand")
(match_operand:DI 2 "immediate_operand")
(match_operand:DI 3 "immediate_operand")]
"!STRICT_ALIGNMENT"
{
if (aarch64_expand_movmem (operands))
DONE;
FAIL;
}
)
;; Operands 1 and 3 are tied together by the final condition; so we allow
;; fairly lax checking on the second memory operation.
(define_insn "load_pairsi"
[(set (match_operand:SI 0 "register_operand" "=r,*w")
(match_operand:SI 1 "aarch64_mem_pair_operand" "Ump,Ump"))
(set (match_operand:SI 2 "register_operand" "=r,*w")
(match_operand:SI 3 "memory_operand" "m,m"))]
"rtx_equal_p (XEXP (operands[3], 0),
plus_constant (Pmode,
XEXP (operands[1], 0),
GET_MODE_SIZE (SImode)))"
"@
ldp\\t%w0, %w2, %1
ldp\\t%s0, %s2, %1"
[(set_attr "type" "load2,neon_load1_2reg")
(set_attr "fp" "*,yes")]
)
(define_insn "load_pairdi"
[(set (match_operand:DI 0 "register_operand" "=r,*w")
(match_operand:DI 1 "aarch64_mem_pair_operand" "Ump,Ump"))
(set (match_operand:DI 2 "register_operand" "=r,*w")
(match_operand:DI 3 "memory_operand" "m,m"))]
"rtx_equal_p (XEXP (operands[3], 0),
plus_constant (Pmode,
XEXP (operands[1], 0),
GET_MODE_SIZE (DImode)))"
"@
ldp\\t%x0, %x2, %1
ldp\\t%d0, %d2, %1"
[(set_attr "type" "load2,neon_load1_2reg")
(set_attr "fp" "*,yes")]
)
;; Operands 0 and 2 are tied together by the final condition; so we allow
;; fairly lax checking on the second memory operation.
(define_insn "store_pairsi"
[(set (match_operand:SI 0 "aarch64_mem_pair_operand" "=Ump,Ump")
(match_operand:SI 1 "aarch64_reg_or_zero" "rZ,*w"))
(set (match_operand:SI 2 "memory_operand" "=m,m")
(match_operand:SI 3 "aarch64_reg_or_zero" "rZ,*w"))]
"rtx_equal_p (XEXP (operands[2], 0),
plus_constant (Pmode,
XEXP (operands[0], 0),
GET_MODE_SIZE (SImode)))"
"@
stp\\t%w1, %w3, %0
stp\\t%s1, %s3, %0"
[(set_attr "type" "store2,neon_store1_2reg")
(set_attr "fp" "*,yes")]
)
(define_insn "store_pairdi"
[(set (match_operand:DI 0 "aarch64_mem_pair_operand" "=Ump,Ump")
(match_operand:DI 1 "aarch64_reg_or_zero" "rZ,*w"))
(set (match_operand:DI 2 "memory_operand" "=m,m")
(match_operand:DI 3 "aarch64_reg_or_zero" "rZ,*w"))]
"rtx_equal_p (XEXP (operands[2], 0),
plus_constant (Pmode,
XEXP (operands[0], 0),
GET_MODE_SIZE (DImode)))"
"@
stp\\t%x1, %x3, %0
stp\\t%d1, %d3, %0"
[(set_attr "type" "store2,neon_store1_2reg")
(set_attr "fp" "*,yes")]
)
;; Operands 1 and 3 are tied together by the final condition; so we allow
;; fairly lax checking on the second memory operation.
(define_insn "load_pairsf"
[(set (match_operand:SF 0 "register_operand" "=w,*r")
(match_operand:SF 1 "aarch64_mem_pair_operand" "Ump,Ump"))
(set (match_operand:SF 2 "register_operand" "=w,*r")
(match_operand:SF 3 "memory_operand" "m,m"))]
"rtx_equal_p (XEXP (operands[3], 0),
plus_constant (Pmode,
XEXP (operands[1], 0),
GET_MODE_SIZE (SFmode)))"
"@
ldp\\t%s0, %s2, %1
ldp\\t%w0, %w2, %1"
[(set_attr "type" "neon_load1_2reg,load2")
(set_attr "fp" "yes,*")]
)
(define_insn "load_pairdf"
[(set (match_operand:DF 0 "register_operand" "=w,*r")
(match_operand:DF 1 "aarch64_mem_pair_operand" "Ump,Ump"))
(set (match_operand:DF 2 "register_operand" "=w,*r")
(match_operand:DF 3 "memory_operand" "m,m"))]
"rtx_equal_p (XEXP (operands[3], 0),
plus_constant (Pmode,
XEXP (operands[1], 0),
GET_MODE_SIZE (DFmode)))"
"@
ldp\\t%d0, %d2, %1
ldp\\t%x0, %x2, %1"
[(set_attr "type" "neon_load1_2reg,load2")
(set_attr "fp" "yes,*")]
)
;; Operands 0 and 2 are tied together by the final condition; so we allow
;; fairly lax checking on the second memory operation.
(define_insn "store_pairsf"
[(set (match_operand:SF 0 "aarch64_mem_pair_operand" "=Ump,Ump")
(match_operand:SF 1 "aarch64_reg_or_fp_zero" "w,*rY"))
(set (match_operand:SF 2 "memory_operand" "=m,m")
(match_operand:SF 3 "aarch64_reg_or_fp_zero" "w,*rY"))]
"rtx_equal_p (XEXP (operands[2], 0),
plus_constant (Pmode,
XEXP (operands[0], 0),
GET_MODE_SIZE (SFmode)))"
"@
stp\\t%s1, %s3, %0
stp\\t%w1, %w3, %0"
[(set_attr "type" "neon_store1_2reg,store2")
(set_attr "fp" "yes,*")]
)
(define_insn "store_pairdf"
[(set (match_operand:DF 0 "aarch64_mem_pair_operand" "=Ump,Ump")
(match_operand:DF 1 "aarch64_reg_or_fp_zero" "w,*rY"))
(set (match_operand:DF 2 "memory_operand" "=m,m")
(match_operand:DF 3 "aarch64_reg_or_fp_zero" "w,*rY"))]
"rtx_equal_p (XEXP (operands[2], 0),
plus_constant (Pmode,
XEXP (operands[0], 0),
GET_MODE_SIZE (DFmode)))"
"@
stp\\t%d1, %d3, %0
stp\\t%x1, %x3, %0"
[(set_attr "type" "neon_store1_2reg,store2")
(set_attr "fp" "yes,*")]
)
;; Load pair with post-index writeback. This is primarily used in function
;; epilogues.
(define_insn "loadwb_pair_"
[(parallel
[(set (match_operand:P 0 "register_operand" "=k")
(plus:P (match_operand:P 1 "register_operand" "0")
(match_operand:P 4 "aarch64_mem_pair_offset" "n")))
(set (match_operand:GPI 2 "register_operand" "=r")
(mem:GPI (match_dup 1)))
(set (match_operand:GPI 3 "register_operand" "=r")
(mem:GPI (plus:P (match_dup 1)
(match_operand:P 5 "const_int_operand" "n"))))])]
"INTVAL (operands[5]) == GET_MODE_SIZE (mode)"
"ldp\\t%2, %3, [%1], %4"
[(set_attr "type" "load2")]
)
(define_insn "loadwb_pair_"
[(parallel
[(set (match_operand:P 0 "register_operand" "=k")
(plus:P (match_operand:P 1 "register_operand" "0")
(match_operand:P 4 "aarch64_mem_pair_offset" "n")))
(set (match_operand:GPF 2 "register_operand" "=w")
(mem:GPF (match_dup 1)))
(set (match_operand:GPF 3 "register_operand" "=w")
(mem:GPF (plus:P (match_dup 1)
(match_operand:P 5 "const_int_operand" "n"))))])]
"INTVAL (operands[5]) == GET_MODE_SIZE (mode)"
"ldp\\t%2, %3, [%1], %4"
[(set_attr "type" "neon_load1_2reg")]
)
;; Store pair with pre-index writeback. This is primarily used in function
;; prologues.
(define_insn "storewb_pair_"
[(parallel
[(set (match_operand:P 0 "register_operand" "=&k")
(plus:P (match_operand:P 1 "register_operand" "0")
(match_operand:P 4 "aarch64_mem_pair_offset" "n")))
(set (mem:GPI (plus:P (match_dup 0)
(match_dup 4)))
(match_operand:GPI 2 "register_operand" "r"))
(set (mem:GPI (plus:P (match_dup 0)
(match_operand:P 5 "const_int_operand" "n")))
(match_operand:GPI 3 "register_operand" "r"))])]
"INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (mode)"
"stp\\t%2, %3, [%0, %4]!"
[(set_attr "type" "store2")]
)
(define_insn "storewb_pair_"
[(parallel
[(set (match_operand:P 0 "register_operand" "=&k")
(plus:P (match_operand:P 1 "register_operand" "0")
(match_operand:P 4 "aarch64_mem_pair_offset" "n")))
(set (mem:GPF (plus:P (match_dup 0)
(match_dup 4)))
(match_operand:GPF 2 "register_operand" "w"))
(set (mem:GPF (plus:P (match_dup 0)
(match_operand:P 5 "const_int_operand" "n")))
(match_operand:GPF 3 "register_operand" "w"))])]
"INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (mode)"
"stp\\t%2, %3, [%0, %4]!"
[(set_attr "type" "neon_store1_2reg")]
)
;; -------------------------------------------------------------------
;; Sign/Zero extension
;; -------------------------------------------------------------------
(define_expand "sidi2"
[(set (match_operand:DI 0 "register_operand")
(ANY_EXTEND:DI (match_operand:SI 1 "nonimmediate_operand")))]
""
)
(define_insn "*extendsidi2_aarch64"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
""
"@
sxtw\t%0, %w1
ldrsw\t%0, %1"
[(set_attr "type" "extend,load1")]
)
(define_insn "*load_pair_extendsidi2_aarch64"
[(set (match_operand:DI 0 "register_operand" "=r")
(sign_extend:DI (match_operand:SI 1 "aarch64_mem_pair_operand" "Ump")))
(set (match_operand:DI 2 "register_operand" "=r")
(sign_extend:DI (match_operand:SI 3 "memory_operand" "m")))]
"rtx_equal_p (XEXP (operands[3], 0),
plus_constant (Pmode,
XEXP (operands[1], 0),
GET_MODE_SIZE (SImode)))"
"ldpsw\\t%0, %2, %1"
[(set_attr "type" "load2")]
)
(define_insn "*zero_extendsidi2_aarch64"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
""
"@
uxtw\t%0, %w1
ldr\t%w0, %1"
[(set_attr "type" "extend,load1")]
)
(define_insn "*load_pair_zero_extendsidi2_aarch64"
[(set (match_operand:DI 0 "register_operand" "=r")
(zero_extend:DI (match_operand:SI 1 "aarch64_mem_pair_operand" "Ump")))
(set (match_operand:DI 2 "register_operand" "=r")
(zero_extend:DI (match_operand:SI 3 "memory_operand" "m")))]
"rtx_equal_p (XEXP (operands[3], 0),
plus_constant (Pmode,
XEXP (operands[1], 0),
GET_MODE_SIZE (SImode)))"
"ldp\\t%w0, %w2, %1"
[(set_attr "type" "load2")]
)
(define_expand "2"
[(set (match_operand:GPI 0 "register_operand")
(ANY_EXTEND:GPI (match_operand:SHORT 1 "nonimmediate_operand")))]
""
)
(define_insn "*extend2_aarch64"
[(set (match_operand:GPI 0 "register_operand" "=r,r")
(sign_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand" "r,m")))]
""
"@
sxt\t%0, %w1
ldrs\t%0, %1"
[(set_attr "type" "extend,load1")]
)
(define_insn "*zero_extend2_aarch64"
[(set (match_operand:GPI 0 "register_operand" "=r,r,*w")
(zero_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand" "r,m,m")))]
""
"@
and\t%0, %1,
ldr\t%w0, %1
ldr\t%0, %1"
[(set_attr "type" "logic_imm,load1,load1")]
)
(define_expand "qihi2"
[(set (match_operand:HI 0 "register_operand")
(ANY_EXTEND:HI (match_operand:QI 1 "nonimmediate_operand")))]
""
)
(define_insn "*extendqihi2_aarch64"
[(set (match_operand:HI 0 "register_operand" "=r,r")
(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
""
"@
sxtb\t%w0, %w1
ldrsb\t%w0, %1"
[(set_attr "type" "extend,load1")]
)
(define_insn "*zero_extendqihi2_aarch64"
[(set (match_operand:HI 0 "register_operand" "=r,r")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
""
"@
and\t%w0, %w1, 255
ldrb\t%w0, %1"
[(set_attr "type" "logic_imm,load1")]
)
;; -------------------------------------------------------------------
;; Simple arithmetic
;; -------------------------------------------------------------------
(define_expand "add3"
[(set
(match_operand:GPI 0 "register_operand" "")
(plus:GPI (match_operand:GPI 1 "register_operand" "")
(match_operand:GPI 2 "aarch64_pluslong_operand" "")))]
""
{
/* If operands[1] is a subreg extract the inner RTX. */
rtx op1 = REG_P (operands[1]) ? operands[1] : SUBREG_REG (operands[1]);
/* If the constant is too large for a single instruction and isn't frame
based, split off the immediate so it is available for CSE. */
if (!aarch64_plus_immediate (operands[2], mode)
&& can_create_pseudo_p ()
&& (!REG_P (op1)
|| !REGNO_PTR_FRAME_P (REGNO (op1))))
operands[2] = force_reg (mode, operands[2]);
})
(define_insn "*add3_aarch64"
[(set
(match_operand:GPI 0 "register_operand" "=rk,rk,w,rk,r")
(plus:GPI
(match_operand:GPI 1 "register_operand" "%rk,rk,w,rk,rk")
(match_operand:GPI 2 "aarch64_pluslong_operand" "I,r,w,J,Upl")))]
""
"@
add\\t%0, %1, %2
add\\t%0, %1, %2
add\\t%0, %1, %2
sub\\t%0, %1, #%n2
#"
[(set_attr "type" "alu_imm,alu_sreg,neon_add,alu_imm,multiple")
(set_attr "simd" "*,*,yes,*,*")]
)
;; zero_extend version of above
(define_insn "*addsi3_aarch64_uxtw"
[(set
(match_operand:DI 0 "register_operand" "=rk,rk,rk,r")
(zero_extend:DI
(plus:SI (match_operand:SI 1 "register_operand" "%rk,rk,rk,rk")
(match_operand:SI 2 "aarch64_pluslong_operand" "I,r,J,Upl"))))]
""
"@
add\\t%w0, %w1, %2
add\\t%w0, %w1, %w2
sub\\t%w0, %w1, #%n2
#"
[(set_attr "type" "alu_imm,alu_sreg,alu_imm,multiple")]
)
;; If there's a free register, and we can load the constant with a
;; single instruction, do so. This has a chance to improve scheduling.
(define_peephole2
[(match_scratch:GPI 3 "r")
(set (match_operand:GPI 0 "register_operand")
(plus:GPI
(match_operand:GPI 1 "register_operand")
(match_operand:GPI 2 "aarch64_pluslong_strict_immedate")))]
"aarch64_move_imm (INTVAL (operands[2]), mode)"
[(set (match_dup 3) (match_dup 2))
(set (match_dup 0) (plus:GPI (match_dup 1) (match_dup 3)))]
)
(define_peephole2
[(match_scratch:SI 3 "r")
(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
(plus:SI
(match_operand:SI 1 "register_operand")
(match_operand:SI 2 "aarch64_pluslong_strict_immedate"))))]
"aarch64_move_imm (INTVAL (operands[2]), SImode)"
[(set (match_dup 3) (match_dup 2))
(set (match_dup 0) (zero_extend:DI (plus:SI (match_dup 1) (match_dup 3))))]
)
;; After peephole2 has had a chance to run, split any remaining long
;; additions into two add immediates.
(define_split
[(set (match_operand:GPI 0 "register_operand")
(plus:GPI
(match_operand:GPI 1 "register_operand")
(match_operand:GPI 2 "aarch64_pluslong_strict_immedate")))]
"epilogue_completed"
[(set (match_dup 0) (plus:GPI (match_dup 1) (match_dup 3)))
(set (match_dup 0) (plus:GPI (match_dup 0) (match_dup 4)))]
{
HOST_WIDE_INT i = INTVAL (operands[2]);
HOST_WIDE_INT s = (i >= 0 ? i & 0xfff : -(-i & 0xfff));
operands[3] = GEN_INT (i - s);
operands[4] = GEN_INT (s);
}
)
(define_split
[(set (match_operand:DI 0 "register_operand")
(zero_extend:DI
(plus:SI
(match_operand:SI 1 "register_operand")
(match_operand:SI 2 "aarch64_pluslong_strict_immedate"))))]
"epilogue_completed"
[(set (match_dup 5) (plus:SI (match_dup 1) (match_dup 3)))
(set (match_dup 0) (zero_extend:DI (plus:SI (match_dup 5) (match_dup 4))))]
{
HOST_WIDE_INT i = INTVAL (operands[2]);
HOST_WIDE_INT s = (i >= 0 ? i & 0xfff : -(-i & 0xfff));
operands[3] = GEN_INT (i - s);
operands[4] = GEN_INT (s);
operands[5] = gen_lowpart (SImode, operands[0]);
}
)
(define_expand "addti3"
[(set (match_operand:TI 0 "register_operand" "")
(plus:TI (match_operand:TI 1 "register_operand" "")
(match_operand:TI 2 "register_operand" "")))]
""
{
rtx low = gen_reg_rtx (DImode);
emit_insn (gen_adddi3_compareC (low, gen_lowpart (DImode, operands[1]),
gen_lowpart (DImode, operands[2])));
rtx high = gen_reg_rtx (DImode);
emit_insn (gen_adddi3_carryin (high, gen_highpart (DImode, operands[1]),
gen_highpart (DImode, operands[2])));
emit_move_insn (gen_lowpart (DImode, operands[0]), low);
emit_move_insn (gen_highpart (DImode, operands[0]), high);
DONE;
})
(define_insn "add3_compare0"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(plus:GPI (match_operand:GPI 1 "register_operand" "%r,r,r")
(match_operand:GPI 2 "aarch64_plus_operand" "r,I,J"))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r,r,r")
(plus:GPI (match_dup 1) (match_dup 2)))]
""
"@
adds\\t%0, %1, %2
adds\\t%0, %1, %2
subs\\t%0, %1, #%n2"
[(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
)
;; zero_extend version of above
(define_insn "*addsi3_compare0_uxtw"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(plus:SI (match_operand:SI 1 "register_operand" "%r,r,r")
(match_operand:SI 2 "aarch64_plus_operand" "r,I,J"))
(const_int 0)))
(set (match_operand:DI 0 "register_operand" "=r,r,r")
(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
""
"@
adds\\t%w0, %w1, %w2
adds\\t%w0, %w1, %2
subs\\t%w0, %w1, #%n2"
[(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
)
(define_insn "*add3_compareC_cconly_imm"
[(set (reg:CC_C CC_REGNUM)
(ne:CC_C
(plus:
(zero_extend: (match_operand:GPI 0 "register_operand" "r,r"))
(match_operand: 2 "const_scalar_int_operand" ""))
(zero_extend:
(plus:GPI
(match_dup 0)
(match_operand:GPI 1 "aarch64_plus_immediate" "I,J")))))]
"aarch64_zero_extend_const_eq (mode, operands[2],
mode, operands[1])"
"@
cmn\\t%0, %1
cmp\\t%0, #%n1"
[(set_attr "type" "alus_imm")]
)
(define_insn "*add3_compareC_cconly"
[(set (reg:CC_C CC_REGNUM)
(ne:CC_C
(plus:
(zero_extend: (match_operand:GPI 0 "register_operand" "r"))
(zero_extend: (match_operand:GPI 1 "register_operand" "r")))
(zero_extend: (plus:GPI (match_dup 0) (match_dup 1)))))]
""
"cmn\\t%0, %1"
[(set_attr "type" "alus_sreg")]
)
(define_insn "*add3_compareC_imm"
[(set (reg:CC_C CC_REGNUM)
(ne:CC_C
(plus:
(zero_extend: (match_operand:GPI 1 "register_operand" "r,r"))
(match_operand: 3 "const_scalar_int_operand" ""))
(zero_extend:
(plus:GPI
(match_dup 1)
(match_operand:GPI 2 "aarch64_plus_immediate" "I,J")))))
(set (match_operand:GPI 0 "register_operand" "=r,r")
(plus:GPI (match_dup 1) (match_dup 2)))]
"aarch64_zero_extend_const_eq (mode, operands[3],
mode, operands[2])"
"@
adds\\t%0, %1, %2
subs\\t%0, %1, #%n2"
[(set_attr "type" "alus_imm")]
)
(define_insn "add3_compareC"
[(set (reg:CC_C CC_REGNUM)
(ne:CC_C
(plus:
(zero_extend: (match_operand:GPI 1 "register_operand" "r"))
(zero_extend: (match_operand:GPI 2 "register_operand" "r")))
(zero_extend:
(plus:GPI (match_dup 1) (match_dup 2)))))
(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (match_dup 1) (match_dup 2)))]
""
"adds\\t%0, %1, %2"
[(set_attr "type" "alus_sreg")]
)
(define_insn "*adds_shift_imm_"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(plus:GPI (ASHIFT:GPI
(match_operand:GPI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_shift_imm_" "n"))
(match_operand:GPI 3 "register_operand" "r"))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (ASHIFT:GPI (match_dup 1) (match_dup 2))
(match_dup 3)))]
""
"adds\\t%0, %3, %1, %2"
[(set_attr "type" "alus_shift_imm")]
)
(define_insn "*subs_shift_imm_"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(minus:GPI (match_operand:GPI 1 "register_operand" "r")
(ASHIFT:GPI
(match_operand:GPI 2 "register_operand" "r")
(match_operand:QI 3 "aarch64_shift_imm_" "n")))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r")
(minus:GPI (match_dup 1)
(ASHIFT:GPI (match_dup 2) (match_dup 3))))]
""
"subs\\t%0, %1, %2, %3"
[(set_attr "type" "alus_shift_imm")]
)
(define_insn "*adds_mul_imm_"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(plus:GPI (mult:GPI
(match_operand:GPI 1 "register_operand" "r")
(match_operand:QI 2 "aarch64_pwr_2_" "n"))
(match_operand:GPI 3 "register_operand" "r"))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (mult:GPI (match_dup 1) (match_dup 2))
(match_dup 3)))]
""
"adds\\t%0, %3, %1, lsl %p2"
[(set_attr "type" "alus_shift_imm")]
)
(define_insn "*subs_mul_imm_"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(minus:GPI (match_operand:GPI 1 "register_operand" "r")
(mult:GPI
(match_operand:GPI 2 "register_operand" "r")
(match_operand:QI 3 "aarch64_pwr_2_" "n")))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r")
(minus:GPI (match_dup 1)
(mult:GPI (match_dup 2) (match_dup 3))))]
""
"subs\\t%0, %1, %2, lsl %p3"
[(set_attr "type" "alus_shift_imm")]
)
(define_insn "*adds__"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(plus:GPI
(ANY_EXTEND:GPI (match_operand:ALLX 1 "register_operand" "r"))
(match_operand:GPI 2 "register_operand" "r"))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (ANY_EXTEND:GPI (match_dup 1)) (match_dup 2)))]
""
"adds\\t%0, %2, %1, xt"
[(set_attr "type" "alus_ext")]
)
(define_insn "*subs__"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(minus:GPI (match_operand:GPI 1 "register_operand" "r")
(ANY_EXTEND:GPI
(match_operand:ALLX 2 "register_operand" "r")))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r")
(minus:GPI (match_dup 1) (ANY_EXTEND:GPI (match_dup 2))))]
""
"subs\\t%0, %1, %2, xt"
[(set_attr "type" "alus_ext")]
)
(define_insn "*adds__shift_"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(plus:GPI (ashift:GPI
(ANY_EXTEND:GPI
(match_operand:ALLX 1 "register_operand" "r"))
(match_operand 2 "aarch64_imm3" "Ui3"))
(match_operand:GPI 3 "register_operand" "r"))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=rk")
(plus:GPI (ashift:GPI (ANY_EXTEND:GPI (match_dup 1))
(match_dup 2))
(match_dup 3)))]
""
"adds\\t%0, %3, %1, xt %2"
[(set_attr "type" "alus_ext")]
)
(define_insn "*subs__shift_"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(minus:GPI (match_operand:GPI 1 "register_operand" "r")
(ashift:GPI
(ANY_EXTEND:GPI
(match_operand:ALLX 2 "register_operand" "r"))
(match_operand 3 "aarch64_imm3" "Ui3")))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=rk")
(minus:GPI (match_dup 1)
(ashift:GPI (ANY_EXTEND:GPI (match_dup 2))
(match_dup 3))))]
""
"subs\\t%0, %1, %2, xt %3"
[(set_attr "type" "alus_ext")]
)
(define_insn "*adds__multp2"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(plus:GPI (ANY_EXTRACT:GPI
(mult:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand 2 "aarch64_pwr_imm3" "Up3"))
(match_operand 3 "const_int_operand" "n")
(const_int 0))
(match_operand:GPI 4 "register_operand" "r"))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r")
(plus:GPI (ANY_EXTRACT:GPI (mult:GPI (match_dup 1) (match_dup 2))
(match_dup 3)
(const_int 0))
(match_dup 4)))]
"aarch64_is_extend_from_extract (mode, operands[2], operands[3])"
"adds\\t%0, %4, %1, xt%e3 %p2"
[(set_attr "type" "alus_ext")]
)
(define_insn "*subs__multp2"
[(set (reg:CC_NZ CC_REGNUM)
(compare:CC_NZ
(minus:GPI (match_operand:GPI 4 "register_operand" "r")
(ANY_EXTRACT:GPI
(mult:GPI (match_operand:GPI 1 "register_operand" "r")
(match_operand 2 "aarch64_pwr_imm3" "Up3"))
(match_operand 3 "const_int_operand" "n")
(const_int 0)))
(const_int 0)))
(set (match_operand:GPI 0 "register_operand" "=r")
(minus:GPI (match_dup 4) (ANY_EXTRACT:GPI
(mult:GPI (match_dup 1) (match_dup 2))
(match_dup 3)
(const_int 0))))]
"aarch64_is_extend_from_extract (mode, operands[2], operands[3])"
"subs\\t%