From 2e85eb0e4950c5ad27df5a3ba54300e89694eba4 Mon Sep 17 00:00:00 2001 From: Dave Stevenson Date: Mon, 9 Sep 2024 17:38:45 +0100 Subject: [PATCH 1347/1350] drm/vc4: Drop panic priority for writeback connector As the writeback connector doesn't have the same realtime constraints of a live display, drop the panic priority for it. Signed-off-by: Dave Stevenson --- drivers/gpu/drm/vc4/vc4_kms.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) --- a/drivers/gpu/drm/vc4/vc4_kms.c +++ b/drivers/gpu/drm/vc4/vc4_kms.c @@ -224,7 +224,7 @@ static void vc4_hvs_pv_muxing_commit(str struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); u32 dispctrl; - u32 dsp3_mux; + u32 dsp3_mux_pri; if (!crtc_state->active) continue; @@ -241,15 +241,22 @@ static void vc4_hvs_pv_muxing_commit(str * enabled. In this case, FIFO 2 is directly accessed by the * TXP IP, and we need to disable the FIFO2 -> pixelvalve1 * route. + * + * TXP can also run with a lower panic level than a live display, + * as it doesn't have the same real-time constraint. */ - if (vc4_crtc->feeds_txp) - dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX); - else - dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX); + if (vc4_crtc->feeds_txp) { + dsp3_mux_pri = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX); + dsp3_mux_pri |= VC4_SET_FIELD(0, SCALER_DISPCTRL_PANIC2); + } else { + dsp3_mux_pri = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX); + dsp3_mux_pri |= VC4_SET_FIELD(2, SCALER_DISPCTRL_PANIC2); + } dispctrl = HVS_READ(SCALER_DISPCTRL) & - ~SCALER_DISPCTRL_DSP3_MUX_MASK; - HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux); + ~(SCALER_DISPCTRL_DSP3_MUX_MASK | + SCALER_DISPCTRL_PANIC2_MASK); + HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux_pri); } }