# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Display DSI 10nm PHY

maintainers:
  - Krishna Manikandan <mkrishn@codeaurora.org>

allOf:
  - $ref: dsi-phy-common.yaml#

properties:
  compatible:
    enum:
      - qcom,dsi-phy-10nm
      - qcom,dsi-phy-10nm-8998

  reg:
    items:
      - description: dsi phy register set
      - description: dsi phy lane register set
      - description: dsi pll register set

  reg-names:
    items:
      - const: dsi_phy
      - const: dsi_phy_lane
      - const: dsi_pll

  vdds-supply:
    description: |
      Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
      connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target

required:
  - compatible
  - reg
  - reg-names

unevaluatedProperties: false

examples:
  - |
     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
     #include <dt-bindings/clock/qcom,rpmh.h>

     dsi-phy@ae94400 {
         compatible = "qcom,dsi-phy-10nm";
         reg = <0x0ae94400 0x200>,
               <0x0ae94600 0x280>,
               <0x0ae94a00 0x1e0>;
         reg-names = "dsi_phy",
                     "dsi_phy_lane",
                     "dsi_pll";

         #clock-cells = <1>;
         #phy-cells = <0>;

         vdds-supply = <&vdda_mipi_dsi0_pll>;
         clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
                  <&rpmhcc RPMH_CXO_CLK>;
         clock-names = "iface", "ref";
     };
...